1. Field of the Invention
This invention relates to a counter element for constructing synchronous modulo-n or 2.sup.m counters having a storage member, which is constructed of a master-slave flip-flop wherein a circuit for performing a majority decision of two variables in conjunction with the output of the slave is connected directly to one input of the master and indirectly to the other input by way of an inverter so that the storage member operates in accordance with the truth table
S R Qto Qtl ______________________________________ L O O O L L O L O L L L O O L O L O L L L L L L O L O O O O O O ______________________________________
the truth table corresponding to the Boolean equation EQU Qt1 = S .sup.. R + Qto .sup.. (S + R).
2. description of the Prior Art
Synchronous modulo-n counters do not have a decade structure. These counters count in a dual code up to the number n and then resume counting. The number of the counting elements required for a modulo-n counter can be determined from the number raised to the power two so that the expression 2.sup.m .gtoreq. n applies. In this relationship m constitutes the number of required counting elements. There are not only counter circuits which have a single preferred counting direction in counting techniques, but also counter circuits which, via an additional control input counting operations can be switched from forward to backward counting and vice versa. These counting circuits generally require a considerable amount of additional switching means in addition to the actual counting elements, also called counter flip-flops. Basically, synchronous modulo 2.sup.m counters are constructed from a number of counter elements and constitute dual code counters which can count numbers raised to the power of two. These counters can be of particularly simple structure. The two mentioned types of counters are synchronous counters since the counting elements of the same counter switch in response to the same pulse.